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Please use this identifier to cite or link to this item: http://dspace.utalca.cl/handle/1950/9396

Title: FPGA v/s DSP Performance Comparison for a VSC-Based STATCOM Control Application
Authors: Sepulveda, C.A.
Munoz, J.A.;
Espinoza, J.R.
Figueroa, M.E.
Baier, C.R.
Keywords: Digital control
digital signal processor (DSP)
Digital control; digital signal processor (DSP); field-programmable gate array (FPGA); Static Compensator (STATCOM)
Static Compensator (STATCOM)
Issue Date: Aug-2013
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Citation: Source: IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS Volume: 9 Issue: 3 Pages: 1351-1360 DOI: 10.1109/TII.2012.2222419
Abstract: Digital signal processors (DSPs) and field-programmable gate arrays (FPGAs) are predominant in the implementation of digital controllers and/or modulators for power converter applications. This paper presents a systematic comparison between these two technologies, depicting the main advantages and drawbacks of each one. Key programming and implementation aspects are addressed in order to give an overall idea of their most important features and allow the comparison between DSP and FPGA devices. A classical linear control strategy for a well-known voltage-source-converter (VSC)-based topology used as Static Compensator (STATCOM) is considered as a driving example to evaluate the performance of both approaches. A proof-of-concept laboratory prototype is separately controlled with the TMS320F2812 DSP and the Spartan-3 XCS1000 FPGA to illustrate the characteristics of both technologies. In the case of the DSP, a virtual floating-point library is used to accelerate the control routines compared to double precision arithmetic. On the other hand, two approaches are developed for the FPGA implementation, the first one reduces the hardware utilization and the second one reduces the computation time. Even though both boards can successfully control the STATCOM, results show that the FPGA achieves the best computation time thanks to the high degree of parallelism available on the device.
Description: Munoz, JA (Munoz, Javier A.); Baier, CR (Baier, Carlos R.). Univ Talca, Dept Ind Technol, Talca 747C, Chile
URI: http://dspace.utalca.cl/handle/1950/9396
ISSN: 1551-3203
Appears in Collections:Artículos en publicaciones ISI - Universidad de Talca

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